> Other than increased miniaturization, the most striking change is the use of copper pours [...] Why did we start doing this?
We've been doing something a lot like this for as long as I can remember.
Back in the 1990s if there were any big unused copper areas on your PCB you'd mask them to save on etching acid - a gallon of acid would have a lifetime measured in square inches of copper removed, and the less copper you removed, the longer your acid would last.
Meanwhile, a lot of DIY etching processes were very basic. Sure, you could get translucent acid and a transparent bath and heat it to a controlled temperature and run bubbles through it and so on. But if you were on a budget, some room temperature ferric chloride in an old ice cream container would get the job done. And getting the etch resist onto the board? You could draw it by hand with special pens, use transfers, there were special printer toner transfer papers, or you could DIY UV photoresist using printable projector transparencies and the sun as your UV source.
This was not a super-scientific, tightly controlled process.
If you had narrow traces and narrow gaps on one part of your PCB, and large areas of copper to remove on another? Well, if you left it in the acid long enough to remove that large area, could be the narrow traces get etched away too.
So masking off any large areas meant all the copper getting etched was about the same width - thus compensating for the poorly controlled etching process.
Of course, these days professional PCB manufacturing is orders of magnitude cheaper than it used to be. When you send your design to pcbway or jlcpcb they have much tighter control over the process, so you no longer have to worry about this stuff.
> When you send your design to pcbway or jlcpcb they have much tighter control over the process, so you no longer have to worry about this stuff.
Funny that you mention jlcpcb. The last time I submitted a board with tight differential pairs (but still within their listed specs) to them they basically told me to increase the amount of copper, so I assume they had some quality issues in the past:
> we have new rule since Dec, 2022, if the copper areas are less than 30% of the board in each copper layer, the space between trace and trace should be at least 0.15mm to avoid short circuit.
So I had to add a few copper pours and everything was fine :)
Well, you may not have to worry, but if you have large unpoured areas on a design with a professional PCB manufacturer (of the traditional, high-touch kind), they will ask if you want to pour some copper there. Reason being that it makes the process faster, more consistent and reduce possible side-etching on lanes. It may not a make a difference in most cases, but you may just save some time and effort by doing this.
> The return current on the back is free to spread out, but in practice, it will prefer the path of least resistance — i.e., the shortest line between the two vias.
This is a bit misleading. It does preferentially flow along the shortest path, but not exclusively. It will indeed spread out. It takes all paths with a current proportional to their resistance, not just the shortest path. The percentage of total current that isn't flowing directly along the shortest path is still very significant.
Think of it as a bunch of resistors in parallel. The shortest path might be 0.1ohm, and the longest path 10x longer at 1ohm, but current will be flowing along both of those paths. If 1A is flowing down the shortest path, you will still have 100mA down the 10x length path.
I don't know anything about electricity so this intrigued me. Is it related to the "proximity effect" [0]? Is it caused because of the fact that the magnetic field created by high-frequency current is always changing, so this induces a voltage in any nearby conductor?
One of my all time favorite videos (one of the few that I rewatch once per year) is "The Extreme Importance of PC Board Stack-Up with Rick Hartley". It's fantastic.
Grumble grumble. Professional here, and I really do not like this article.
There are a lot of things getting mixed up here: ground planes for EMC, ground planes for electrical performance, ground planes for DFM/etching, and ground planes as "fashion".
First off, let's just say that meeting radiated EMC ("47 CFR Part 15" according to the article, equivalent to CISPR 22/32 in Europe) is a bloody good idea. Yes, the testing labs are "a bit of a racket". But does anyone else remember the days when turning on the vacuum cleaner would knock out the TV? That wasn't great. And we have a whole lot more electronics in the world today. A world without Part 15/CISPR is an ugly world indeed.
Four-layer boards are cheap. Really cheap. They may be double the cost, but you're doubling pennies here. In fact, just checking in with one common low-volume supplier, they're not doubling: the price for 200mm × 100mm boards with good specs goes from $9.34 each in quantity 10 to... $10.59. For prototypes, that's basically a rounding error. Perhaps even literally a rounding error. So don't complain about the cost of four-layer boards anymore, it isn't 2004.
Internal ground fill layers are what people usually mean when talking about "ground planes". They have three key properties:
1. They are very easy to do and are very tolerant of mistakes. You don't have to calculate return current paths, you don't have to size and locate return current traces, you don't have to gum up your routing. You just dedicate the layer and it works, and it keeps working if you have to make changes later.
2. They help shield internal layers further down in the stack from radiating. This is usually minor, but for nasty digital stuff or high-power electronics, can be useful.
3. They develop inter-plane capacitance with nearby power layers, if inter-layer dielectrics are small. This is critical to maintaining power distribution network performance at high frequencies (>100s of MHz). This stuff is very, very important to make high-speed digital logic work well. Of course, it's only one link in the chain (GHz stuff gets handled on-package or even on-die; <100MHz is the job of on-board capacitors until you get into power supply dynamics in the kHz and below). This is the "increasing shunt capacitance" mentioned in the article. Yes, it can be bad news for analog stuff, but this is both very rare and the sort of problem where anyone who can do that kind of difficult analog design has the skill to punch a hole in the plane where it's needed.
There is also a manufacturing issue where the manufacturers find it easiest to have approximately balanced amounts of copper on opposite layers of a board. Copper pours are one solution to this. Copper thieving pads are another. This is important but easy to manage, and vendors are good at it.
So all of the above applies to internal layer copper fills. None of it is "fashion": there are good reasons to do it, the extra layers are cheap these days, and it's an easy and robust way to design things. Fills on external layers are a different matter; they're kind of stupid in a lot of cases. Unless you're doing a two-layer design, or a 4-layer that kind of ends up behaving like a 2-layer (this happens sometimes when stuff is very tight), the external fills are pretty worthless. I wrote more about this ages ago over here: https://www.eevblog.com/forum/eda/altium-article-on-never-us... This is the only real thing I'd agree with the article on.
There's a lot of stuff going on here, and I don't think this article does a very good job keeping it straight. If you take one thing away from all of this, it should probably be that internal copper planes are pretty great, and what happens on the outside of the board isn't so important.
A reason for more external copper pours might also be that the EDA tools have improved and can now handle the complex shapes. Back in the 80s/90s copper pours were a pain using Protel (later called Altium), as they were built using straight tracks rather than polygons. Eventually the program got actual polygons and life became easier.
Piggybacking onto this comment, but another reason for external pours is thermal performance. A copper pour on the surface on the PCB allows heat to convect off the board more easily. The gains aren't massive, but they can help as part of a larger thermal management scheme.
I've also heard, possibly apocryphally, that in the old days when we used harsher chemical etchants, removing all of the copper from unused sections of the PCB would increase the risk of thinning the traces beyond what was intended. So in those cases a copper pour would reduce the time the PCB would need to spend in the etchant bath.
Going by the inconsistent spacing and angles on that 1984 PCB, I'd almost guarantee that it was routed using black tape on mylar film, not a CAD package to be seen. Trying to create large fills back then would require manual positioning of tape over all of the copper fill areas. Tools is a big part of the reason for the shift, it's easy now, and the results are generally much better.
I actually prefer using plane layers with tracks to split to the messiness of polygon pours. It signals design intent to users and fab houses and doesn't require a ton of rules and calculations. Polygon pours have their place in top/bottom power nets.
"There's a lot of stuff going on here, and I don't think this article does a very good job keeping it straight. If you take one thing away from all of this, it should probably be that internal copper planes are pretty great, and what happens on the outside of the board isn't so important."
And then this article totally ignores solid metal PCBs, which are my realm of specialty and have their own inherent challenges when it comes to digital equipment.
The default today is likely signal/ground/ground/signal.
Or really, the default today is a 6 layer board because 4 is still kinda bad.
Today's engineers know that signal-top has a return path through ground-top. But if you ever were to via a wire from signal-top to signal-bottom, the return path gets lost (aka: return path is now through the board or worse, through the air and radiating off of your board).
To prevent this erratic behavior, you must continue to think about the return path and tie a via from ground-top to ground-bottom as close as possible to the via between signal-top and signal-bottom.
--------
6 layer can do signal/ground/signal -core- signal/ground/signal
Where core is the FR4 material (keeping the middle signals far enough apart that they likely don't interfere with each other). This allows vias between layer#1 and #3 without needing a secondary return via. (But if you need layer#1 to layer#6 via, then the previous advice still applies where ground-top needs a secondary return via to ground-bottom).
The default should be X / GND / X GND to maintain tight coupling of both signals and power to the GND plane and stitch the GND planes together with vias close to any other via that changes layers to maintain return paths.
Power should be routed normally, except it should use widest practical traces and get decoupled with C close to ICs that consume it.
But in any case, you always need to think about the signal and return. Even for power. It's never truly DC.
If you do the "classic" signals / GND / VDD / signals, you are routing over VDD plane and your ground is waaay farther. Means all accidental VDD noise (you can't pinpoint, because it takes frequency dependent paths across the VDD/GND C) gets coupled into your signals on the back side.
If you put the power planes on the inner layers and the signal on the outer layers, it's much easier to visually inspect the signal layers. And if you got something wrong on the prototype and you have to fix it manually, the traces are right there where you can get at them.
On the other hand, if you're doing some performance-critical RF wizardry, you might put the ground planes on the outer layers and the signal on the inner layers, sandwiching your signal between two ground planes. So if you look at a wifi module or something like that, sometimes the outer layers will have very few traces.
Yep. And then for 6 layers, depending on the actual needs of the design, it'll often be components/ground/signal or power/signal or power/ground/components. Some designs need a lot of signal routing space. Some need a lot of split power rails. And some are nice and easy and don't need either.
If you don't need components on the bottom side, it saves money to not do so. That means the board doesn't need to go through another pass on the SMT machine.
Even if a board is double-sided, it is common to avoid putting major ICs on both sides, unless the space constraints are severe. Often, people will only put passive components on the bottom side.
A bit related: we developed CapExt for extracting parasitic capacitances and resistances on PCBs and 3D models. It’s mainly for capacitive touch applications, but it could also help in cases like this, where copper pours and ground planes are in play.
If anyone’s curious, you can check it out here: capext.com
I don't think the article's audience are professional EEs/PCB designers otherwise they'd know all of this stuff and then some. So anyone serious should probably seek out a better reference.
That's a reasonable take, but in my opinion, is not what a non-expert reading of this article seems to be suggesting. So I wanted to state the alternative case.
> To keep things simple, some hobbyists opt for four-layer boards, with the two inner layers dedicated to GND and Vdd. This works, but means paying about twice as much.
With the prices out of Shenzhen, there is IMO no reason to use a 2-layer board, outside of trivial cases (Like a CAN terminator etc). 4-layers are a bit more expensive, but make routing much easier. I don't want to spend the time solving the routing puzzle on a two-layer board, then worrying about inductance (the article's topic) on top of that.
Baseline 2024 plan: Start with 4-layers as a generic baseline. Go to 6 (or higher?) if your design is sufficiently complex, and/or complex. (Or has high-frequency signals). More layers = more easier.
The simple explanation is that glue logic and wide busses have mostly disappeared from contemporary electronics. Now you have a smattering of peripherals with point to point links leaving board space for fills that would have been pointless attempting with pervasive Manhattan routing on the outer layers.
Solid fills also had a propensity to warp boards, requiring hatched patterns to relieve the imbalance. That constrained their use to boards with sufficient free space to maintain connectivity of the fill areas. PCB manufacturing has improved enough to minimize this concern.
> In electronic circuits, the flow of electrons is confined to conductors, but the transfer of energy doesn’t involve these particles bouncing off each other; instead, the process is mediated through electromagnetic fields. These fields originate from charge carriers, but extend freely into the surrounding space.
That's a great couple of sentences; it really clearly explains what's going on.
I don't see it mentioned here but I may be too much of an amateur but I use copper pours because it reduces the work my ferric chloride has to do when I'm making prototypes. Having a mask cover all unused areas on the board vs. letting the acid eat through it seems like a waste.
Your logic is definitely sound for a hobbyist or prototyped, but the copper dissolved off a board in a commercial setting is recycled.
The article misses the real reason why pours were uncommon in the 80s, which is that people had to actually “tape out” the whole thing, and it was very annoying to do pours that way.
Readit News
We've been doing something a lot like this for as long as I can remember.
Back in the 1990s if there were any big unused copper areas on your PCB you'd mask them to save on etching acid - a gallon of acid would have a lifetime measured in square inches of copper removed, and the less copper you removed, the longer your acid would last.
Meanwhile, a lot of DIY etching processes were very basic. Sure, you could get translucent acid and a transparent bath and heat it to a controlled temperature and run bubbles through it and so on. But if you were on a budget, some room temperature ferric chloride in an old ice cream container would get the job done. And getting the etch resist onto the board? You could draw it by hand with special pens, use transfers, there were special printer toner transfer papers, or you could DIY UV photoresist using printable projector transparencies and the sun as your UV source.
This was not a super-scientific, tightly controlled process.
If you had narrow traces and narrow gaps on one part of your PCB, and large areas of copper to remove on another? Well, if you left it in the acid long enough to remove that large area, could be the narrow traces get etched away too.
So masking off any large areas meant all the copper getting etched was about the same width - thus compensating for the poorly controlled etching process.
Of course, these days professional PCB manufacturing is orders of magnitude cheaper than it used to be. When you send your design to pcbway or jlcpcb they have much tighter control over the process, so you no longer have to worry about this stuff.
Funny that you mention jlcpcb. The last time I submitted a board with tight differential pairs (but still within their listed specs) to them they basically told me to increase the amount of copper, so I assume they had some quality issues in the past:
> we have new rule since Dec, 2022, if the copper areas are less than 30% of the board in each copper layer, the space between trace and trace should be at least 0.15mm to avoid short circuit.
So I had to add a few copper pours and everything was fine :)
This is a bit misleading. It does preferentially flow along the shortest path, but not exclusively. It will indeed spread out. It takes all paths with a current proportional to their resistance, not just the shortest path. The percentage of total current that isn't flowing directly along the shortest path is still very significant.
Think of it as a bunch of resistors in parallel. The shortest path might be 0.1ohm, and the longest path 10x longer at 1ohm, but current will be flowing along both of those paths. If 1A is flowing down the shortest path, you will still have 100mA down the 10x length path.
[0]: https://www.sciencedirect.com/topics/computer-science/proxim...
https://resources.altium.com/p/the-extreme-importance-of-pc-...
There are a lot of things getting mixed up here: ground planes for EMC, ground planes for electrical performance, ground planes for DFM/etching, and ground planes as "fashion".
First off, let's just say that meeting radiated EMC ("47 CFR Part 15" according to the article, equivalent to CISPR 22/32 in Europe) is a bloody good idea. Yes, the testing labs are "a bit of a racket". But does anyone else remember the days when turning on the vacuum cleaner would knock out the TV? That wasn't great. And we have a whole lot more electronics in the world today. A world without Part 15/CISPR is an ugly world indeed.
Four-layer boards are cheap. Really cheap. They may be double the cost, but you're doubling pennies here. In fact, just checking in with one common low-volume supplier, they're not doubling: the price for 200mm × 100mm boards with good specs goes from $9.34 each in quantity 10 to... $10.59. For prototypes, that's basically a rounding error. Perhaps even literally a rounding error. So don't complain about the cost of four-layer boards anymore, it isn't 2004.
Internal ground fill layers are what people usually mean when talking about "ground planes". They have three key properties:
1. They are very easy to do and are very tolerant of mistakes. You don't have to calculate return current paths, you don't have to size and locate return current traces, you don't have to gum up your routing. You just dedicate the layer and it works, and it keeps working if you have to make changes later.
2. They help shield internal layers further down in the stack from radiating. This is usually minor, but for nasty digital stuff or high-power electronics, can be useful.
3. They develop inter-plane capacitance with nearby power layers, if inter-layer dielectrics are small. This is critical to maintaining power distribution network performance at high frequencies (>100s of MHz). This stuff is very, very important to make high-speed digital logic work well. Of course, it's only one link in the chain (GHz stuff gets handled on-package or even on-die; <100MHz is the job of on-board capacitors until you get into power supply dynamics in the kHz and below). This is the "increasing shunt capacitance" mentioned in the article. Yes, it can be bad news for analog stuff, but this is both very rare and the sort of problem where anyone who can do that kind of difficult analog design has the skill to punch a hole in the plane where it's needed.
There is also a manufacturing issue where the manufacturers find it easiest to have approximately balanced amounts of copper on opposite layers of a board. Copper pours are one solution to this. Copper thieving pads are another. This is important but easy to manage, and vendors are good at it.
So all of the above applies to internal layer copper fills. None of it is "fashion": there are good reasons to do it, the extra layers are cheap these days, and it's an easy and robust way to design things. Fills on external layers are a different matter; they're kind of stupid in a lot of cases. Unless you're doing a two-layer design, or a 4-layer that kind of ends up behaving like a 2-layer (this happens sometimes when stuff is very tight), the external fills are pretty worthless. I wrote more about this ages ago over here: https://www.eevblog.com/forum/eda/altium-article-on-never-us... This is the only real thing I'd agree with the article on.
There's a lot of stuff going on here, and I don't think this article does a very good job keeping it straight. If you take one thing away from all of this, it should probably be that internal copper planes are pretty great, and what happens on the outside of the board isn't so important.
I've also heard, possibly apocryphally, that in the old days when we used harsher chemical etchants, removing all of the copper from unused sections of the PCB would increase the risk of thinning the traces beyond what was intended. So in those cases a copper pour would reduce the time the PCB would need to spend in the etchant bath.
And then this article totally ignores solid metal PCBs, which are my realm of specialty and have their own inherent challenges when it comes to digital equipment.
Or really, the default today is a 6 layer board because 4 is still kinda bad.
Today's engineers know that signal-top has a return path through ground-top. But if you ever were to via a wire from signal-top to signal-bottom, the return path gets lost (aka: return path is now through the board or worse, through the air and radiating off of your board).
To prevent this erratic behavior, you must continue to think about the return path and tie a via from ground-top to ground-bottom as close as possible to the via between signal-top and signal-bottom.
--------
6 layer can do signal/ground/signal -core- signal/ground/signal
Where core is the FR4 material (keeping the middle signals far enough apart that they likely don't interfere with each other). This allows vias between layer#1 and #3 without needing a secondary return via. (But if you need layer#1 to layer#6 via, then the previous advice still applies where ground-top needs a secondary return via to ground-bottom).
The default should be X / GND / X GND to maintain tight coupling of both signals and power to the GND plane and stitch the GND planes together with vias close to any other via that changes layers to maintain return paths.
Power should be routed normally, except it should use widest practical traces and get decoupled with C close to ICs that consume it.
But in any case, you always need to think about the signal and return. Even for power. It's never truly DC.
If you do the "classic" signals / GND / VDD / signals, you are routing over VDD plane and your ground is waaay farther. Means all accidental VDD noise (you can't pinpoint, because it takes frequency dependent paths across the VDD/GND C) gets coupled into your signals on the back side.
So don't do that.
If you put the power planes on the inner layers and the signal on the outer layers, it's much easier to visually inspect the signal layers. And if you got something wrong on the prototype and you have to fix it manually, the traces are right there where you can get at them.
On the other hand, if you're doing some performance-critical RF wizardry, you might put the ground planes on the outer layers and the signal on the inner layers, sandwiching your signal between two ground planes. So if you look at a wifi module or something like that, sometimes the outer layers will have very few traces.
Even if a board is double-sided, it is common to avoid putting major ICs on both sides, unless the space constraints are severe. Often, people will only put passive components on the bottom side.
Deleted Comment
If anyone’s curious, you can check it out here: capext.com
> To keep things simple, some hobbyists opt for four-layer boards, with the two inner layers dedicated to GND and Vdd. This works, but means paying about twice as much.
With the prices out of Shenzhen, there is IMO no reason to use a 2-layer board, outside of trivial cases (Like a CAN terminator etc). 4-layers are a bit more expensive, but make routing much easier. I don't want to spend the time solving the routing puzzle on a two-layer board, then worrying about inductance (the article's topic) on top of that.
Baseline 2024 plan: Start with 4-layers as a generic baseline. Go to 6 (or higher?) if your design is sufficiently complex, and/or complex. (Or has high-frequency signals). More layers = more easier.
Solid fills also had a propensity to warp boards, requiring hatched patterns to relieve the imbalance. That constrained their use to boards with sufficient free space to maintain connectivity of the fill areas. PCB manufacturing has improved enough to minimize this concern.
Deleted Comment
That's a great couple of sentences; it really clearly explains what's going on.
The article misses the real reason why pours were uncommon in the 80s, which is that people had to actually “tape out” the whole thing, and it was very annoying to do pours that way.