>I expect the same for 7nm. Both 12nm and 7nm will be much more affordable in 2020. Right now the uncertainty is 5nm and 3nm. Both are technically achievable, the problem is cost. At the moment 5nm+ cost structure looks like exclusive to certain industry and clients. [1]
That was my oldest comment I could find on HN made in 2017. Although my projection was made on Anandtech some time around 2016.
I was originally projecting a slow down to 3 years cadence post 5nm at 3 / 2nm. But at the time there were no "Trillion Dollar" company and AI wasn't a thing. I was also at the time ignorant of HyperScaler's volume.
Even if all of that will allow us to go further, 2nm in 2025, 1.4nm in 2027 and 1nm in 2029 / 2030. Surely the hypotheses remains, that at some point the market will not be able to justify the cost of new node. And will have to amortized over a longer period of time.
At 1nm, if it were to cost $30K per Wafer, a 100mm die would cost $50 at 100% yield. That is excluding the potential $2 - $3B design cost.
Your first link prices per chip makes it look like it's about 71 chips per wafer for 5nm at $238 per chip. If we get the same number of chips per wafer at 2nm, that's about $350 per chip.
I'm always a little skeptical of seeking alpha article by <name> covering a report by company owned/run by <name>. There's no information whatsoever about how these estimates were generated. I'm sure you could back them out with decent accuracy from earnings statements, but the industry is notoriously secretive. I don't think there's any way he can even fathom a guess at what the price will be for N2.
It's also worth mentioning that none of the big players will be paying sticker price. They negotiate contracts that pay per KGD (known good die) since the process yields are abysmal for the first year or two.
There are plenty of reputable one-man analyst shops. Presumably they have inside information gathered by "informally" talking to many people in the industry.
I think this is a bit where Intel has an opportunity to catch up a bit. 3nm is costing 40% more than 5nm and we'll see how long it will take AMD to move to 3nm. It took AMD 2 years to move to 5nm after Apple started shipping 5nm phones.
Intel is set to launch Meteor Lake on Intel 4 later this year or early 2024. That will put AMD and Intel on a similar process-level footing. If Intel can get Intel 20A out the door around the same time TSMC gets 2nm out the door, we might see Intel overtake AMD on process. Intel's latest roadmap has 20A in the "2023-2024" time frame which seems a tad unlikely at this point and 18A for "2024+". It's possible that Intel will get ahead of TSMC on process if they actually hit their roadmap given that TSMC is looking at 2025 for 2nm. In that case, AMD might be facing a tough battle.
If Intel can control its costs better than TSMC's charges, that will make a big difference. If TSMC's charges for 2nm are going to be 75% more than 5nm, that's going to eat into margins for someone like AMD.
However, while Intel does seem to be making some good moves today, it's probably too soon to completely buy into their roadmap. Yes, they're refocusing their culture in a positive direction. It's still reasonable to have some doubt on Intel's roadmap.
Intel has already lost Apple. ARM has not been very successful on Windows yet, but Nuvia hased processors are supposed to be launched end of this year. If Nuvia chip is anything close to M1 also then both Intel and AMD are going to have tough time.
Intel has already lost its role as chip provider with Apple. As a fab, if it outperforms TSMC as the parent suggests, it could provide manufacturing for Apple's designs.
Of course, we'll have to see if Intel keeps up after finally clearing its 10nm hurdle.
The M series isn't as great as it seemed. It had an initial advantage of a smaller node, and benefits from everything being on-die. It's huge, so it relies more on the chip tech getting smaller than traditional CPU solutions.
Why assume that Intel's cost at this resolution is anything less than TSMC's? It likely will be much more expensive for Intel as they lack the experience and are producing in a country with higher basic costs than Taiwan.
The Ryzen 7940HS, which is a pretty good value, is on TSMC 4nm, rumored to already cost close to $20k/wafer.
Even if they double the transistor count, a single SKU should theoretically be cheaper to produce, since you're reducing the footprint by 4. Of course, this is assuming yields don't fall too badly on 2nm (which they probably will, 2nm feels like alien technology at this point).
Has the number of chips produced from a single wafer (assuming same wafer size) changed from what they call 5nm to 2nm? I know that's hard to quantify, you basically have to start a new architecture from scratch when a new node comes out.
I'm curious if the price increase isn't as bad as it seems because of that, but IANAE.
In any case, I suppose this was expected. TSMC is on the bleeding edge of technology, and the techniques and equipment that make all of this possible is absurdly astounding. It's a miracle of modern cooperation and science that any of it works at all.
Prices will go down as the process matures, and we all see progress march forward. Win-win to me.
According to the graph on the linked page below, the cost per transistor hit a minimum at 28nm (which was the last of the planar designs), and has risen slightly with FinFET (which is not as reliable as planar).
"The chart below is from Marvell’s 2020 investor day. The bar for 28nm was approximately 2011-2012."
If you scroll down to the table you can see the trend. New process node price increases far outpace price drops for mature nodes. Price per transistor has been stagnating since 2012 but it's only becoming significant now.
The worst part is that MCM doesn't even solve this problem, actually in some ways it makes it worse. MCM solves yield not wafer cost - people conflate the two into a single die cost number but they're actually two distinct things really.
Take RDNA3 as an example. Even if you get 100% yields, you need a significant amount of additional area in the product. N31 is over 500mm2 of area even if it's yielded as a 308mm2 chiplet and six 38mm2 chiplets. Even if all of those yield at 100% you can't make it not be 500mm2 of area, and you have to pay for that.
And because MCM imposes some performance overheads that have to be compensated for, and because of the innate nature of the additional PHYs taking up area, the actual total area is larger than a monolithic chip. This is an offsetting factor in the comparison to monolithic, yes monolithic yields lower but it also needs less actual silicon too, and that pushes yields back up a touch and pushes wafer cost down a touch.
Comparisons between products are always inexact, and NVIDIA is on a slightly different node (a customized version of N4/N5P called 4N) but it's the same general family (AMD is on N5P) and 7900XTX is using 531mm2 total to compete with the 4080 which uses only 378mm2 - so we are talking about potentially a 40% area overhead for MCM, which is significant in terms of increased wafer cost even if the yields are higher.
Even if you assume RDNA3 missed expectations and "should" have performed somewhat better... we are still probably talking about a >20% area advantage for monolithic products.
(and, note that rumors have swirled recently that N4 and N5P are actually the same thing, they have the same density and library. Reportedly, both TSMC and Samsung faked their N4 and 4LPX libraries for marketing reasons and pushed the "true" node off, in the same way that TSMC kinda pushed off the real N3 into N3E (e for enhanced) and called the shitty version N3B (b for bad) instead... so N4 vs N5P for the basis of the 4N custom nodelet may not actually be a meaningful distinction after all, lol. And RDNA3 and Ada may actually be on the same parent node as a result.)
Anyway, it is the same thing in CPUs too - yes, the CCD/IO die approach is great, but, it also does use a lot more silicon than a monolithic chip would for an equivalent design. Epyc has 8 or 16 chiplets of N5P and another giant chiplet of N6 for the IO die. That's a lot of total area, and wafer costs continue to increase.
The other place it bites is in GPU dies too. PHYs don't shrink, and there are de-facto "minimums" of 4 PHYs per GPU (of any performance) imposed by actual raw bandwidth requirements and the need for 8GB of VRAM (current max is 2GB/16gbit per module unless you go clamshell, which drives up cost a ton). Every time you shrink, the wafer cost of that fixed, non-shrinkable PHY area goes up by 25% or 50%, even if you yield that area at 100%, and the performance does not increase accordingly. This is what's been eating up the gains in the low-end dGPU market, and this is the reason AMD chose not to shrink RX 7600 / Navi33 to N5P with the rest of the lineup and left it on N6 instead.
Thermals are the elephant in the room with stacking and wafer costs are the elephant in the room with MCM and PHYs. Yes, yields are better, but it doesn't mean the wafers are free either.
You can fit more chip in the same space with a die shrink. It's not as much more as it used to be, but it is more. N2 is still pretty new so I'm not privy to details about how much.
Has the number of chips produced from a single wafer (assuming same wafer size) changed from what they call 5nm to 2nm?
Most companies target the same die size across generations. For example, AMD CCDs have been close to 80 mm2 for three generations and Apple keeps the A-class die size around 100 mm2.
I haven't heard what the mask costs are for 2nm or 3nm. For TSMC 5nm the masks are about $30 million. If you have a bug and can fix it with a metal only change then it is about $20 million. I can assure you thought that they will be more expensive for 3 and 2nm.
If you are making a huge chip that is close to the max reticle size then you can't share it with anyone.
When I have done shuttle runs they split the reticle into 4x4mm sections and each cost about $100,000 in 28nm. I think the full 28nm mask set was a few million dollars back in 2012 when it was current technology. You could get another size in multiples of 4 like 4x8mm or 8x8mm where you paid another $100K for each 4x4 section.
But you can't use these shuttle masks when you are going to full production where you make millions of chips because you would be making chips from other company's next to yours and that company may have had bugs in that mask or only want 100,000 chips while you want a million.
The masks are a one time cost (assuming you don't have any bugs which is rare) but that is a huge portion of the NRE (Non Recurring Engineering cost or one time cost)
1 atom of Cesium is .26nm (largest). 2nm is at the granularity level of 8 Cesium atoms! For Silicon .11) we are talking about transistors made of 18 atoms (roughly?)?
My question is, do they factor in a significant transisyor failure rate and silently reroute or something or are things actually stable enough to survive years of real world usage without transistor failure becoming an issue?
I'd like to see the table they list there adjusted on a $/transistor rate. 7nm is ~1/3 the cost of 2nm, but if you can fit 3x as many transistors on 2nm then it could be a wash...
Readit News
https://www.siliconexpert.com/blog/tsmc-3nm-wafer/
That was my oldest comment I could find on HN made in 2017. Although my projection was made on Anandtech some time around 2016.
I was originally projecting a slow down to 3 years cadence post 5nm at 3 / 2nm. But at the time there were no "Trillion Dollar" company and AI wasn't a thing. I was also at the time ignorant of HyperScaler's volume.
Even if all of that will allow us to go further, 2nm in 2025, 1.4nm in 2027 and 1nm in 2029 / 2030. Surely the hypotheses remains, that at some point the market will not be able to justify the cost of new node. And will have to amortized over a longer period of time.
At 1nm, if it were to cost $30K per Wafer, a 100mm die would cost $50 at 100% yield. That is excluding the potential $2 - $3B design cost.
[1] https://news.ycombinator.com/item?id=14835609
It's also worth mentioning that none of the big players will be paying sticker price. They negotiate contracts that pay per KGD (known good die) since the process yields are abysmal for the first year or two.
Intel is set to launch Meteor Lake on Intel 4 later this year or early 2024. That will put AMD and Intel on a similar process-level footing. If Intel can get Intel 20A out the door around the same time TSMC gets 2nm out the door, we might see Intel overtake AMD on process. Intel's latest roadmap has 20A in the "2023-2024" time frame which seems a tad unlikely at this point and 18A for "2024+". It's possible that Intel will get ahead of TSMC on process if they actually hit their roadmap given that TSMC is looking at 2025 for 2nm. In that case, AMD might be facing a tough battle.
If Intel can control its costs better than TSMC's charges, that will make a big difference. If TSMC's charges for 2nm are going to be 75% more than 5nm, that's going to eat into margins for someone like AMD.
However, while Intel does seem to be making some good moves today, it's probably too soon to completely buy into their roadmap. Yes, they're refocusing their culture in a positive direction. It's still reasonable to have some doubt on Intel's roadmap.
They didn't have much choice. Apple booked most of the production capacity for those two years:
https://www.notebookcheck.net/Apple-secures-80-percent-of-TS...
Of course, we'll have to see if Intel keeps up after finally clearing its 10nm hurdle.
The M series isn't as great as it seemed. It had an initial advantage of a smaller node, and benefits from everything being on-die. It's huge, so it relies more on the chip tech getting smaller than traditional CPU solutions.
Who’s going to write a “Rosetta for Windows” that works seamlessly though?
The Ryzen 7940HS, which is a pretty good value, is on TSMC 4nm, rumored to already cost close to $20k/wafer.
Even if they double the transistor count, a single SKU should theoretically be cheaper to produce, since you're reducing the footprint by 4. Of course, this is assuming yields don't fall too badly on 2nm (which they probably will, 2nm feels like alien technology at this point).
TSMC N2 is estimated to be something like 30% denser than N4.
I'm curious if the price increase isn't as bad as it seems because of that, but IANAE.
In any case, I suppose this was expected. TSMC is on the bleeding edge of technology, and the techniques and equipment that make all of this possible is absurdly astounding. It's a miracle of modern cooperation and science that any of it works at all.
Prices will go down as the process matures, and we all see progress march forward. Win-win to me.
"The chart below is from Marvell’s 2020 investor day. The bar for 28nm was approximately 2011-2012."
Cost is per 100 million gates.
https://www.fabricatedknowledge.com/p/the-rising-tide-of-sem...Take RDNA3 as an example. Even if you get 100% yields, you need a significant amount of additional area in the product. N31 is over 500mm2 of area even if it's yielded as a 308mm2 chiplet and six 38mm2 chiplets. Even if all of those yield at 100% you can't make it not be 500mm2 of area, and you have to pay for that.
And because MCM imposes some performance overheads that have to be compensated for, and because of the innate nature of the additional PHYs taking up area, the actual total area is larger than a monolithic chip. This is an offsetting factor in the comparison to monolithic, yes monolithic yields lower but it also needs less actual silicon too, and that pushes yields back up a touch and pushes wafer cost down a touch.
Comparisons between products are always inexact, and NVIDIA is on a slightly different node (a customized version of N4/N5P called 4N) but it's the same general family (AMD is on N5P) and 7900XTX is using 531mm2 total to compete with the 4080 which uses only 378mm2 - so we are talking about potentially a 40% area overhead for MCM, which is significant in terms of increased wafer cost even if the yields are higher.
Even if you assume RDNA3 missed expectations and "should" have performed somewhat better... we are still probably talking about a >20% area advantage for monolithic products.
https://en.wikipedia.org/wiki/List_of_AMD_graphics_processin...
https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_proces...
(and, note that rumors have swirled recently that N4 and N5P are actually the same thing, they have the same density and library. Reportedly, both TSMC and Samsung faked their N4 and 4LPX libraries for marketing reasons and pushed the "true" node off, in the same way that TSMC kinda pushed off the real N3 into N3E (e for enhanced) and called the shitty version N3B (b for bad) instead... so N4 vs N5P for the basis of the 4N custom nodelet may not actually be a meaningful distinction after all, lol. And RDNA3 and Ada may actually be on the same parent node as a result.)
https://www.reddit.com/r/hardware/comments/145e9ft/tsmc_n4_i... (actual tweet seems to be removed?)
Anyway, it is the same thing in CPUs too - yes, the CCD/IO die approach is great, but, it also does use a lot more silicon than a monolithic chip would for an equivalent design. Epyc has 8 or 16 chiplets of N5P and another giant chiplet of N6 for the IO die. That's a lot of total area, and wafer costs continue to increase.
The other place it bites is in GPU dies too. PHYs don't shrink, and there are de-facto "minimums" of 4 PHYs per GPU (of any performance) imposed by actual raw bandwidth requirements and the need for 8GB of VRAM (current max is 2GB/16gbit per module unless you go clamshell, which drives up cost a ton). Every time you shrink, the wafer cost of that fixed, non-shrinkable PHY area goes up by 25% or 50%, even if you yield that area at 100%, and the performance does not increase accordingly. This is what's been eating up the gains in the low-end dGPU market, and this is the reason AMD chose not to shrink RX 7600 / Navi33 to N5P with the rest of the lineup and left it on N6 instead.
Thermals are the elephant in the room with stacking and wafer costs are the elephant in the room with MCM and PHYs. Yes, yields are better, but it doesn't mean the wafers are free either.
Most companies target the same die size across generations. For example, AMD CCDs have been close to 80 mm2 for three generations and Apple keeps the A-class die size around 100 mm2.
This says that the 5nm reticle size is 26mm x 33mm
https://fuse.wikichip.org/news/3377/tsmc-announces-2x-reticl...
If you are making a huge chip that is close to the max reticle size then you can't share it with anyone.
When I have done shuttle runs they split the reticle into 4x4mm sections and each cost about $100,000 in 28nm. I think the full 28nm mask set was a few million dollars back in 2012 when it was current technology. You could get another size in multiples of 4 like 4x8mm or 8x8mm where you paid another $100K for each 4x4 section.
But you can't use these shuttle masks when you are going to full production where you make millions of chips because you would be making chips from other company's next to yours and that company may have had bugs in that mask or only want 100,000 chips while you want a million.
The masks are a one time cost (assuming you don't have any bugs which is rare) but that is a huge portion of the NRE (Non Recurring Engineering cost or one time cost)
My question is, do they factor in a significant transisyor failure rate and silently reroute or something or are things actually stable enough to survive years of real world usage without transistor failure becoming an issue?
Is it possible to calculate a cost pr. usable transistor? And how does 2nm compare with its predecessors?