One of the tactics I end up using in Verilog, for better or worse, is to define enums with a'0 value (repeat 0s for the size of the variable), and '1 value (repeat 1s for the size of the value)
'0 stays as "null"-like (e.g INVALID), and '1 (which would be 0xFF in an 8 bit byte for instance) becomes "something, but I'm not sure what" (e.g. UNKNOWN).
Definitely has the same issues as referenced when needing to grow the variable, and the times where it's useful aren't super common, but I do feel like the general concept of an unknown-but-not-invalid value can help with tracking down errors in processing chains Definitely do run into the need to "beware" though with enums for sure.
What's cool is that the Raspberry-PI V is just fast enough to run modern desktop software, including (ack!) Microsoft Teams. I was able to give a live demo of my FPGA design by sharing the desktop during a conference call.
My only complaint is, of course, lack of SoC documentation from Broadcom.
Say what you will about Intel, but they do provide full chip documentation if you go through their NDA process. With it, I made a very nice FPGA PCIe environment on Xeon Ivy Bridge: it let me save all of the PCI config registers, then reconfigure the FPGA, then reprogram them and have the chip show up on the bus without having to reboot the server or re-enumerate. The trick is to temporarily set the root complex bit to disable PCIe error detection during the reconfiguration process.
(Was using Altera Stratix-IIgx at the time).
There is possibly another way to this, but haven't tried it:
https://stackoverflow.com/questions/32334870/how-to-do-a-tru...
But even aside from that, with the documentation you have access to a lot of error reporting which is extremely useful during PCIe bring-up.