Niklaus Wirth is one of those unsung geniuses of computer science. He invented Pascal, the Modulas, Oberon ...
Then he woke up one morning wanting to reboot his life's work for his class and, undeterred by the fact the original targeted processor did not exist anymore, settled to write his own computer architecture on a Xilinx Spartan.
He then successfully ported the Oberon system and compiler to this architecture to demonstrate to his students.
Wirth is one of the rare geniuses who can do the "Things should be as simple as possible, but no simpler." Just reading the code he writes make me feel slightly elevated.
There are bare-metal versions for x86 -- I am running it on a Thinkpad X200 as well as under VirtualBox -- and also versions that run hosted on Windows, 32-bit and 64-bit Linux and Mac OS X.
My website has a long article with A2 running and screenshots for all delivered apps.
Also wort mentioning that Active Oberon has the language features that Oberon lacked for manual memory management in unsafe code and co-routines in the form of active objects, hence its name.
Paco (Active Oberon's compiler) is probably one of the first compilers with parallel phases.
Interesting read! When/how were Oberon systems phased out and replaced (I assume they have been) at the Institute for Computer Systems? It seems to still exist: http://www.cs.inf.ethz.ch/
FWIW there's also a Python emulator for the Wirth RISC. It's slow. It's written to be easy to inspect and trace in a debugger so it does a lot of extra work to "spell out" events in the chip logic. (But if you want speed there's the C emulator, or FPGA!) In any case, the Python emulator will load the disk image and, if you have Pygame installed, it will open a screen window and paint the Oberon Desktop, etc... (It paints it so slowly that you can see the characters fill in as they are drawn!)
>"It is indeed a healthy design paradigm to stick to synchronous circuits in general, if possible. Then, quite obviously, all elements of a circuit operate concurrently, literally at the same time. Every variable and register is defined by one and only one expression combinational circuit). Multiple assignments do not make sense."
I am not quite grokking this and hope someone can explain this to me.
He starts by extolling the merits of sequential logic circuits but then goes on to say that every variable and register need only be a combinatorial circuits. Since these are the two fundamental circuit types, does this point not contradict the earlier one? What am I missing?
Reading further: "In order to simplify an explanation, we restrict our analysis to synchronous circuits — that is, circuits in which all registers tick with the same clock"
Sounds like the author is advocating for designs that do not have derived clocks or gated clocks or multiple clock domains -- all tricky things that designers occasionally do with great care. Clock your flip-flops with the master clock and avoid transparent latches and your design will approach the mathematical ideal that he describes when comparing a circuit to a software program.
I'd guess his Lola HDL restricts you from doing some of these things, where Verilog is more YOLO depending on the vendor and warnings that are enabled.
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Then he woke up one morning wanting to reboot his life's work for his class and, undeterred by the fact the original targeted processor did not exist anymore, settled to write his own computer architecture on a Xilinx Spartan.
He then successfully ported the Oberon system and compiler to this architecture to demonstrate to his students.
Just wow.
I am aware of Oberon and Modula, but had never got a chance to touch them. And that's much more of his work than Pascal.
But it's so niche and windows-centered as to be almost useless. And the community is microscopic.
https://liam-on-linux.livejournal.com/46523.html
This is a good overview:
http://ignorethecode.net/blog/2009/04/22/oberon/
Oberon, a tiny text-oriented OS, evolved into A2, a graphical OS with a zooming UI called Bluebottle. There's some info about A2/Bluebottle here:
http://sage.com.ua/en.shtml?e1l0
Here is the OS on GitHub:
https://github.com/btreut/a2
There are bare-metal versions for x86 -- I am running it on a Thinkpad X200 as well as under VirtualBox -- and also versions that run hosted on Windows, 32-bit and 64-bit Linux and Mac OS X.
Also wort mentioning that Active Oberon has the language features that Oberon lacked for manual memory management in unsafe code and co-routines in the form of active objects, hence its name.
Paco (Active Oberon's compiler) is probably one of the first compilers with parallel phases.
A PDF is here: https://pdfs.semanticscholar.org/d48b/ecdaf5c3d962e2778f804e...
This is essential reading to understand its relevance in computer science.
Oberon is 2 things. It is a language and an OS, or even a family of OSes.
Oberon the language has several versions and works on Linux on x86, x86-64, ARM and other platforms, as well as Windows, BSD, Mac OS X, etc.
E.g. https://github.com/vishaps/voc
Oberon the OS runs on x86 and RISC5 among others. I am considering attempting an ARM port for Raspberry Pi.
So no, it is not at all Windows-centric. One commercial compiler is, but not the language.
It is niche but the community seems quite active.
Former Oberon researchers now work on GraalVM, Go.
The Austrian university which collaborates with Oracle Labs on Graal, used to do Oberon research before switching to Java with Sun Labs.
Java and .NET kind of killed it.
Modula-2 being Oberon's predecessor.
https://github.com/PhoenixBureau/PythonOberon
>"It is indeed a healthy design paradigm to stick to synchronous circuits in general, if possible. Then, quite obviously, all elements of a circuit operate concurrently, literally at the same time. Every variable and register is defined by one and only one expression combinational circuit). Multiple assignments do not make sense."
I am not quite grokking this and hope someone can explain this to me.
He starts by extolling the merits of sequential logic circuits but then goes on to say that every variable and register need only be a combinatorial circuits. Since these are the two fundamental circuit types, does this point not contradict the earlier one? What am I missing?
Sounds like the author is advocating for designs that do not have derived clocks or gated clocks or multiple clock domains -- all tricky things that designers occasionally do with great care. Clock your flip-flops with the master clock and avoid transparent latches and your design will approach the mathematical ideal that he describes when comparing a circuit to a software program.
I'd guess his Lola HDL restricts you from doing some of these things, where Verilog is more YOLO depending on the vendor and warnings that are enabled.
https://en.wikipedia.org/wiki/Sequential_logic
This is not RISCV.
I don't share the joy of others for Plan 9, because for me Inferno is the actual end of the road, Plan 9's architecture with a sane userspace.
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