rajesh-s (u/rajesh-s)

rajesh-s commented on Cache made consistent: Meta’s cache invalidation solution engineering.fb.com/2022/0... · Posted by u/uvdn7

uvdn7 · 3 years ago

I am the author of the blog post. I believe the methodology described should be applicable to most if not all invalidation-based caches. I am serious when I say that cache invalidation might no longer be a hard thing in computer science. AMA!

rajesh-s · 3 years ago

Off topic but what tool did you use to create those cache hierarchy diagrams?

Posted by u/rajesh-s 5 years ago

Ask HN: What are some usecases of real-time collaborative programming?

Posted by u/rajesh-s 5 years ago

Read GitHub code on browser VSCode in less than a second github1s.com/conwnet/gith...

Posted by u/rajesh-s 5 years ago

Ask HN: How to be careful with phishing and domain redirects?

rajesh-s commented on ECC matters realworldtech.com/forum/?... · Posted by u/rajesh-s

GregarianChild · 5 years ago

The paper you cite is from 2014 and the mitigations discussed there have all been circumvented. [1] is from 2020 and a better read for Rowhammer mitigation.

[1] J. S. Kim et al, Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques https://arxiv.org/abs/2005.13121

rajesh-s · 5 years ago

Thanks for pointing that out!

rajesh-s commented on ECC matters realworldtech.com/forum/?... · Posted by u/rajesh-s

theevilsharpie · 5 years ago

ECC isn't a direct mitigation against Rowhammer attacks, as memory errors caused by three or more flipped bits would still go undetected (unless you're using ChipKill, but that's a rare setup).

However, flipped three bits simultaneously isn't trivial, and the attempts that flip fewer bits will be detected and logged.

rajesh-s · 5 years ago

Right! Section 1.3 of this publication discusses possible mitigations for the row hammer problem and where ECC fits in

https://users.ece.cmu.edu/~omutlu/pub/rowhammer-summary.pdf

rajesh-s commented on ECC matters realworldtech.com/forum/?... · Posted by u/rajesh-s

type0 · 5 years ago

Consumer awareness about ECC needs to be better, with recent security implications I simply can't understand why more motherboard manufacturers don't support it on AMD. Intel of course is all to blame on the blue side, I stopped buying their overpriced Xeons because of this.

rajesh-s · 5 years ago

Good point on the need for awareness!

The industry has convinced the average user of consumer hardware that PPA (Power,Performance,Area) is all that needs to get better with generational improvements. Hoping that the concerning aspects of security and reliability that have come to light in the recent past changes this.

rajesh-s commented on ECC matters realworldtech.com/forum/?... · Posted by u/rajesh-s

zdw · 5 years ago

Good news is that for DDR5, ECC is a required part of the spec and should be a feature of every module:

https://www.anandtech.com/show/15912/ddr5-specification-rele...

rajesh-s · 5 years ago

A whitepaper on DDR4 ECC by Micron that goes over some of the implementation challenges

https://media-www.micron.com/-/media/client/global/documents...

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Posted by u/rajesh-s 5 years ago

ECC matters realworldtech.com/forum/?...

u/rajesh-s

KarmaCake day670April 2, 2019

About

Rajesh Shashi Kumar

Hey there! I'm a Computer Engineer interested in Computer Architecture, Systems and Economics.

Twitter: @rajesh_s_

[ my public key: https://keybase.io/rajesh_s; my proof: https://keybase.io/rajesh_s/sigs/zJCAI7WNWJaF-gmiF0e9_NXhy16GJ5R2hs0jKqY5BvQ ]

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