how did it do regalloc before instruction selection? How do you select the correct register class without knowing which instruction you're gonna use?
Readit Newsmshockwave commented on We tasked Opus 4.6 using agent teams to build a C Compiler anthropic.com/engineering... · Posted by u/modeless
mshockwave commented on Banned C++ features in Chromium chromium.googlesource.com... · Posted by u/szmarczak
Intrusive linked lists still firmly have a place in modern code, for reasons other than performance. I don’t know many good reasons for extrusive linked lists, even before caches. There might be a few, but a dynamic array is (and has always been?) usually preferable to an extrusive list.
> I don’t know many good reasons for extrusive linked lists
for one, its iterator won't be invalidated
mshockwave commented on Helion: A high-level DSL for performant and portable ML kernels pytorch.org/blog/helion/... · Posted by u/jarbus
Is it normal to spend 10minutes on tuning nowadays? Do we need to spend another 10 minutes upon changing the code?
mshockwave commented on Swift on FreeBSD Preview forums.swift.org/t/swift-... · Posted by u/glhaynes
> The Swift compiler and runtimes have a few dependencies. Please install the following dependencies:
> (…) python3 (…)
Wait, which part requires Python, and why? And is that only for FreeBSD, or in general? And is that something which will change? Feels very weird that a compiled systems language is dependent on a high-level scripting language.
It's likely that Swift compiler is using LLVM LIT (https://llvm.org/docs/CommandGuide/lit.html), which is implemented in python, as the test driver
This is implemented with instruction fusion. Just need to document properly and publish properly what will end up "standard instruction fusion patterns" (like the div/rem one).
Adding more instructions is kind of non productive for a R(educed)ISC ISA. It has to be weighted with extreme care. Compressed instructions went thru for the sake of code density (marketing vs arm thumb instructions).
In the end, programs will want probably to stay conservative and will implement only the core ISA, at best giving some love to some instruction fusion patterns and that's it, unless being built knowingly for a specific risc-v hardware implementation.
> In the end, programs will want probably to stay conservative and will implement only the core ISA
Unlikely, as pointed out in sibling comments the core ISA is too limited. What might prevail is profiles, specifically profiles for application processors like RVA22U64 and RVA23U64, which the latter one makes a lot more sense IMHO.
mshockwave commented on The Weird Concept of Branchless Programming sanixdk.xyz/blogs/the-wei... · Posted by u/judicious
I've always wondered if any CPUs have tried to reduce the branch penalty by speculatively executing both ways at once in parallel. You'd have two of everything (two pipelines, two ALUs, two sets of registers, etc.) and when you hit a conditional branch, instead of guessing which way to go, you'd essentially fork.
Obviously that requires a lot of extra transistors and you are doing computation that will be thrown away, so it's not free in terms of space or power/heat/energy. But perhaps it could handle cases that other approaches can't.
Even more of a wild idea is to pair up two cores and have them work together this way. When you have a core that would have been idle anyway, it can shadow an active core and be its doppelganger that takes the other branch. You'd need to have very fast communication between cores so the shadow core can spring into action instantly when you hit a branch.
My gut instinct is it's not worth it overall, but I'm curious whether it's been tried in the real world.
yes, it has been done for at least a decade if not more
> Even more of a wild idea is to pair up two cores and have them work together this way
I don't think that'll be profitable, because...
> When you have a core that would have been idle anyway
...you'll just schedule in another process. Modern OS rarely runs short on available tasks to run
mshockwave commented on The Weird Concept of Branchless Programming sanixdk.xyz/blogs/the-wei... · Posted by u/judicious
The article is easy to follow but I think the author missed the e point: branchless programming (a subset of the more known constant time programming) is almost exclusively used in cryptography only nowadays. As shown by the benchmarks in the article, modern branch predictors can easily achieve over 95% if not 99% precision since like a decade ago
But it's really just an implementation difference, the idea is still to have a lightweight RTTI.