Is it normal to spend 10minutes on tuning nowadays? Do we need to spend another 10 minutes upon changing the code?
Readit Newsmshockwave commented on Helion: A high-level DSL for performant and portable ML kernels pytorch.org/blog/helion/... · Posted by u/jarbus
mshockwave commented on Swift on FreeBSD Preview forums.swift.org/t/swift-... · Posted by u/glhaynes
> The Swift compiler and runtimes have a few dependencies. Please install the following dependencies:
> (…) python3 (…)
Wait, which part requires Python, and why? And is that only for FreeBSD, or in general? And is that something which will change? Feels very weird that a compiled systems language is dependent on a high-level scripting language.
It's likely that Swift compiler is using LLVM LIT (https://llvm.org/docs/CommandGuide/lit.html), which is implemented in python, as the test driver
This is implemented with instruction fusion. Just need to document properly and publish properly what will end up "standard instruction fusion patterns" (like the div/rem one).
Adding more instructions is kind of non productive for a R(educed)ISC ISA. It has to be weighted with extreme care. Compressed instructions went thru for the sake of code density (marketing vs arm thumb instructions).
In the end, programs will want probably to stay conservative and will implement only the core ISA, at best giving some love to some instruction fusion patterns and that's it, unless being built knowingly for a specific risc-v hardware implementation.
> In the end, programs will want probably to stay conservative and will implement only the core ISA
Unlikely, as pointed out in sibling comments the core ISA is too limited. What might prevail is profiles, specifically profiles for application processors like RVA22U64 and RVA23U64, which the latter one makes a lot more sense IMHO.
mshockwave commented on The Weird Concept of Branchless Programming sanixdk.xyz/blogs/the-wei... · Posted by u/judicious
I've always wondered if any CPUs have tried to reduce the branch penalty by speculatively executing both ways at once in parallel. You'd have two of everything (two pipelines, two ALUs, two sets of registers, etc.) and when you hit a conditional branch, instead of guessing which way to go, you'd essentially fork.
Obviously that requires a lot of extra transistors and you are doing computation that will be thrown away, so it's not free in terms of space or power/heat/energy. But perhaps it could handle cases that other approaches can't.
Even more of a wild idea is to pair up two cores and have them work together this way. When you have a core that would have been idle anyway, it can shadow an active core and be its doppelganger that takes the other branch. You'd need to have very fast communication between cores so the shadow core can spring into action instantly when you hit a branch.
My gut instinct is it's not worth it overall, but I'm curious whether it's been tried in the real world.
yes, it has been done for at least a decade if not more
> Even more of a wild idea is to pair up two cores and have them work together this way
I don't think that'll be profitable, because...
> When you have a core that would have been idle anyway
...you'll just schedule in another process. Modern OS rarely runs short on available tasks to run
mshockwave commented on The Weird Concept of Branchless Programming sanixdk.xyz/blogs/the-wei... · Posted by u/judicious
The article is easy to follow but I think the author missed the e point: branchless programming (a subset of the more known constant time programming) is almost exclusively used in cryptography only nowadays. As shown by the benchmarks in the article, modern branch predictors can easily achieve over 95% if not 99% precision since like a decade ago
mshockwave commented on Machine Scheduler in LLVM – Part I myhsu.xyz/llvm-machine-sc... · Posted by u/matt_d
"Favor the one with lower register pressure" - my mental model says that register pressure is not a property of a single instruction, but rather depends on when successor instructions will be scheduled.
For example, if an instruction defines a value which has 8 uses, then the "register pressure of the instruction" depends on when those 8 uses will be scheduled.
I guess there is a heuristic to compute the register pressure of an instruction based on a guess of when successors will be scheduled?
yes, the short answer is LLVM uses RegPressureTracker (https://llvm.org/doxygen/classllvm_1_1RegPressureTracker.htm...) to do all those calculations. Slightly longer answer: I should probably be a little more specific that in most cases, Machine Scheduler cares more about register pressure _delta_ caused by a single instruction, either traverses from bottom-up or top-down. In which case it's easier to make an estimation when some of other instructions are not scheduled yet.
mshockwave commented on What if every city had a London Overground? dwell.com/article/what-if... · Posted by u/edward
How did they build those deep tunnels before the invention of TBMs? It must have been slow going.
The scenario suitable for TBM is surprisingly limited so even nowadays many tunnels are still dig using the good’o way, mostly with explosives
I have six animals, and Apple Photos does a great job of recognizing them by name after I labeled them the first time (the office dog as well). Two of them however are gray tabbies (brothers) and it can't distinguish them, so I had to name them with an ampersand ("Harley & Ralph Lauren")
Impressed that it can do as well as it does, I just find that amusing.
Came to say Apple also did a great job on tagging my bois who are both grey-ish cats, even in pictures they faced backward, no idea how they did that