Does Rust provide architecture-specific intrinsics like C/C++ toolchains usually do? That's a popular way to do SIMD.
Yes, in the submodules of `std::arch`
Readit Newskaravelov commented on SIMD programming in pure Rust kerkour.com/introduction-... · Posted by u/randomint64
> […] stops short of recommending some very, very simple steps in aircraft configuration prior to takeoff that would completely mitigate the issue […]
Well, the configuration changes during takeoff mitigate the issue if it happens during takeoff. If it happens at any other time then they don’t do anything to help.
> I can see no reason to drag feet on this recommendation […]
I can. Perhaps the FAA believes that it is better to minimize change fatigue. Since the problem can apparently be fixed in software, and Boeing has decided to make that fix, they might want to write just one airworthiness directive requiring everyone to install it instead of two, one telling pilots to adopt some procedure followed by another telling them to abandon it.
> (It is yet another difference from older 737 design , like the deadly MCAS system, that was not disclosed to pilots transitioning to the new aircraft)
Keep in mind that for most aircraft the airline can pick and choose between different engines. The pilots don’t have to learn the myriad different engineering decisions that go into those engines; from the pilot’s perspective they are supposed to be interchangeable.
> Well, the configuration changes during takeoff mitigate the issue if it happens during takeoff. If it happens at any other time then they don’t do anything to help.
There are no birds at higher altitudes
Waiting for Sabine's comment: "Told you so, physics is dead"
karavelov commented on Intel Meteor Lake Architecture hothardware.com/reviews/i... · Posted by u/SandraBucky
The article (or Intel) do not disclose up to how many cores that new architecture is designed for, and I am certain Intel would say something like "With our P-, E-, LE-cores designed architecture(tm) the core count does matter anymore".
Also the SOC with built-in AI engine. Oh boy, I wonder how long it will take for AI-assisted malware, or botnets to emerge. Exciting times!
It's just 6P + 8E + 2IO (ultra efficient) cores or less. Looks it's primary targeting laptops.
karavelov commented on The State of Async Rust: Runtimes corrode.dev/blog/async/... · Posted by u/RebootStr
I use at least 3 separate runtimes: tokio and 2 no_std runtimes (rtic and embassy). The latter would probably not be possible at all if there was an "official" runtime, because the official runtime would inevitably require allocation, and if it existed they wouldn't bother writing async in a flexible enough way that you could use it without an allocator.
The way async is implemented in rust is actually technically quite impressive, and would almost certainly not exist if there were some official green thread solution.
You could solve async/non-async polymorphism via the introduction of HKTs (and monads) - perhaps eventually they will be forced to do that.
In the mean time, if they can make a few changes like stabilizing TAITs and async traits, that would go a long way to improving the ergos of async.
For interop between runtimes, they need to add `std::async` IO traits that could be implemented by each runtime.
karavelov commented on Grave flaws in BGP Error handling blog.benjojo.co.uk/post/b... · Posted by u/greyface-
> I worry about the state of networking vendors.
> With that being said, I would like to thank the OpenBSD security team, who very rapidly acknowledged my report, and prepared a patch. My only regret with dealing with the OpenBSD team was reporting the issue to them too quickly, as they are uninterested in waiting for any kind of coordination in disclosure.
Lesson to network engineers: switch your routers to OpenBSD/OpenBGPd and keep up on your syspatches to escape this particular hell. ;)
why not switch to bird that was not affected at all? not just acknowledged and fixed. isn’t it “safe be default” better than “fixed after they pointed the flaw”
karavelov commented on Why libvirt supports only 14 PCIe hotplugged devices on x86-64 dottedmag.net/blog/libvir... · Posted by u/andreyvit
I'm curious to know more about the VM host machine that they plugged 15 e1000 cards into to test this limitation. And even more curious about the non-test environment in which somebody ran into this limitation.
I can only imagine trying to passthrough 20 nvme devices to a guest, but it seems like a very weird configuration.
These are emulated `r1000` devices, not pass-through
I was using the same technique back in the day when I was maintaining my Pentax MXs but using a fluorescent lamp as a source - they blink with the AC power cycle - 50 or 60Hz depending on your country.
karavelov commented on ARM vs. Intel on Amazon’s Cloud: A URL Parsing Benchmark lemire.me/blog/2023/03/01... · Posted by u/nnx
We know enough about Apple Silicon to know that high-performance ARM chips aren’t cheap to manufacture.
Until AWS breaks out their margins between X86 and ARM (not going to happen) or total AWS margins start to go down, we don’t really publicly know if they are “dumping” or if they are just passing on the savings to the consumer.
I’d bet that it’s a little of both
The cost of the CPU is small part of a server TCO. Graviton instances could be cheaper because the platform is cheaper, uses less power and needs less cooling - I think we know from Apple Silicon that ARM chips can have these advantages.
Disclaimer: I work for AWS but I don't have any internal knowledge about Graviton pricing and non-public performance data.