Each of those layers can have a cell, so if you have a tlc device at a 100nm pitch, you have a density of 321*3/(1e-4)^2 bits/mm, or about 1e11bits/mm2.
Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or 4e12/mm2 ish.
Not too far away.
https://borecraft.com/files/Comparison_Current_NAND.pdf (from 2019) has some of the cross-sections I was looking for - and that only goes up to 96 layers!
How many layers are needed for each physical cell? Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack.
Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!
15% layoffs is nearly 20,000 people.
15% layoffs is nearly 20,000 people.
Deleted Comment
Has caught out multiple people at my workplace. Feature is buried in the camera pipeline of MacOS, had assumed it was a bug in zoom that it could not be properly disabled - until same thing happened in a msteams call too, so realized it wasn't the zoom feature recognition triggering!
Britain should unironically learn to code.
We’re here quietly - all working for American / multi-national companies. Just little of the Silicon Valley startup culture here in the UK.